module RF8
(
	input wire 			clock         ,
	input wire 			wr_en      ,
	input wire [4:0] 	rd0_addr    ,
	input wire [4:0] 	rs1_addr    ,
	input wire [4:0]	rs2_addr    ,
	input wire [7:0] 	rd0_data    ,
	output reg [7:0] 	rs1_data    ,
	output reg [7:0] 	rs2_data	 
);
wire [7:0]rs1,rs2;
always @(posedge clock ) 
begin
	rs1_data<=rs1;
	rs2_data<=rs2;
end

RegFile RF(
	.clk(clock)         ,
	.wr_en(wr_en)      ,
	.rd0_addr(rd0_addr)    ,
	.rs1_addr(rs1_addr)    ,
	.rs2_addr(rs2_addr)   ,
	.rd0_data(rd0_data)   ,
	.rs1_data(rs1)   ,
	.rs2_data(rs2)	 
) ;

endmodule


module RegFile(
	input wire 			clk         ,
	input wire 			wr_en      ,
	input wire [4:0] 	rd0_addr    ,
	input wire [4:0] 	rs1_addr    ,
	input wire [4:0]	rs2_addr    ,
	input wire [7:0] 	rd0_data    ,
	output wire [7:0] 	rs1_data    ,
	output wire [7:0] 	rs2_data	 
) ;
	reg [7:0] REGFILE [31:1];
	wire w_en ;
assign w_en = ( rd0_addr == 5'b00000 ) ? ( 1'b0 ) : ( wr_en ) ;


always @ ( posedge clk ) begin
	if ( w_en ) begin
		REGFILE [ rd0_addr ] <= rd0_data ;
	end
end

assign rs1_data = (rs1_addr==5'b0)?1'b0 : REGFILE [ rs1_addr ] ;
assign rs2_data = (rs2_addr==5'b0)?1'b0 : REGFILE [ rs2_addr ] ;

endmodule

